Wolfram Sauer
15Patents
7h-index
29Co-inventors
62Inventor score
Filing activity: Jun 20, 1997 → May 5, 2011
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US8037034B2 | Methods of creating a dictionary for data compression | Electricity | 309 | Active |
| US7283072B1 | Methods of creating a dictionary for data compression | Electricity | 182 | Expired |
| US7809933B2 | System and method for optimizing branch logic for handling hard to predict indirect branches | Physics | 42 | Active |
| US7228403B2 | Method for handling 32 bit results for an out-of-order processor with a 64 bit architecture | Physics | 20 | Expired |
| US7627742B2 | Method and apparatus for conserving power by throttling instruction fetching when a processor encounters low confidence branches in an information handling system | Physics | 17 | Active |
| US5930491A | Identification of related instructions resulting from external to internal translation by use of common ID field for each group | Physics | 13 | Expired |
| US6938148B2 | Managing load and store operations using a storage management unit with data flow architecture | Physics | 8 | Expired |
| US7890738B2 | Method and logical apparatus for managing processing system resource use for speculative execution | Emerging Cross-Sectional Technologies | 6 | Active |
| US7460033B2 | Method for creating an in-memory physical dictionary for data compression | Electricity | 2 | Active |
| US7973680B2 | Method and system for creating an in-memory physical dictionary for data compression | Electricity | 1 | Active |
| US7426631B2 | Methods and systems for storing branch information in an address table of a processor | Physics | 1 | Expired |
| US7454597B2 | Computer processing system employing an instruction schedule cache | Physics | 1 | Active |
| US8943301B2 | Storing branch information in an address table of a processor | Physics | 0 | Active |
| US7984280B2 | Storing branch information in an address table of a processor | Physics | 0 | Active |
| US7779234B2 | System and method for implementing a hardware-supported thread assist under load lookahead mechanism for a microprocessor | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.