Petra Leber
37Patents
3h-index
28Co-inventors
63Inventor score
Filing activity: Dec 18, 2001 → Mar 27, 2024
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US7228403B2 | Method for handling 32 bit results for an out-of-order processor with a 64 bit architecture | Physics | 20 | Expired |
| US8291003B2 | Supporting multiple formats in a floating point processor | Physics | 9 | Active |
| US9684514B2 | Inference based condition code generation | Physics | 6 | Active |
| US8346828B2 | System and method for storing numbers in first and second formats in a register file | Physics | 3 | Active |
| US11360769B1 | Decimal scale and convert and split to hexadecimal floating point instruction | Physics | 3 | Active |
| US11023205B2 | Negative zero control in instruction execution | Physics | 2 | Active |
| US9684515B2 | Inference based condition code generation | Physics | 2 | Active |
| US10379860B2 | Inference based condition code generation | Physics | 1 | Active |
| US10915385B2 | Residue prediction of packed data | Physics | 1 | Active |
| US10365892B2 | Decimal floating point instructions to perform directly on compressed decimal floating point data | Physics | 1 | Active |
| US9658828B2 | Decimal and binary floating point rounding | Physics | 1 | Active |
| US11099853B2 | Digit validation check control in instruction execution | Physics | 1 | Active |
| US10996951B2 | Plausibility-driven fault detection in string termination logic for fast exact substring match | Physics | 0 | Active |
| US10198302B2 | Residue prediction of packed data | Physics | 0 | Active |
| US12056465B2 | Verifying the correctness of a leading zero counter | Physics | 0 | Active |
| US9870200B2 | Decimal and binary floating point rounding | Physics | 0 | Active |
| US9128758B2 | Encoding densely packed decimals | Physics | 0 | Active |
| US11314512B2 | Efficient checking of a condition code anticipator for a floating point processor and/or unit | Physics | 0 | Active |
| US10067744B2 | Overflow detection for sign-magnitude adders | Physics | 0 | Active |
| US10929213B2 | Residue prediction of packed data | Physics | 0 | Active |
| US8032854B2 | 3-stack floorplan for floating point unit | Physics | 0 | Active |
| US11861325B2 | Repurposed hexadecimal floating point data path | Physics | 0 | Active |
| US11487506B2 | Condition code anticipator for hexadecimal floating point | Physics | 0 | Active |
| US10095475B2 | Decimal and binary floating point rounding | Physics | 0 | Active |
| US11620153B2 | Instruction interrupt suppression of overflow exception | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.