Method and apparatus for a programmable interface of a soft platform on a programmable logic device
US7228520B1 · kind B1 · utility
18Cited by
12References
24Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 30, 2004 |
| Grant date | Jun 5, 2007 |
| Priority date | — |
| Expiry date | Feb 28, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/34
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Programmable architecture for implementing a message processing system using an integrated circuit is described. In an example, first attributes are defined for a plurality of threads within the integrated circuit. Second attributes are defined for a memory associated with the integrated circuit. Third attributes are defined for an interconnection topology associated with at least one of the memory and the plurality of threads. Fourth attributes are defined for an interface to at least one of the memory and the plurality of threads.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.