Integrated circuit containing polysilicon gate transistors and fully silicidized metal gate transistors
US7229871B2 · kind B2 · utility
7Cited by
4References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 27, 2006 |
| Grant date | Jun 12, 2007 |
| Priority date | — |
| Expiry date | Oct 27, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/668
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for manufacturing an integrated circuit 10 having transistors 20, 30 of two threshold voltages where protected transistor stacks 270 have a gate protection layer 220 that are formed with the use of a single additional mask step. Also, an integrated circuit 10 having at least one polysilicon gate transistor 20 and at least one FUSI metal gate transistor 30.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.