Method and system for inspecting electronic circuit pattern
US7231079B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 18, 2002 |
| Grant date | Jun 12, 2007 |
| Priority date | — |
| Expiry date | Jun 25, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01N2021/8861
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
For the purpose of reducing a false report and shortening inspection time, an area to be inspected is locally inspected under optimum inspection conditions. In order to avoid the number of detected defects from increasing explosively, and thereby to facilitate control of a critical defect, general-purpose layout data, which is used for producing a mask of a semiconductor wafer, is accumulated in a design information server 2. With reference to the layout data, an area to be inspected, which is inspected by a pattern inspecting apparatus 1, is divided into partial inspection areas including a cell portion and a non-cell portion. Inspection parameters are set for each of the partial inspection areas. In addition, the defect reviewing apparatus 8 obtains an inspection result of the pattern inspecting apparatus 1. When obtaining a defect image, the defect reviewing apparatus 8 identifies a position, where the defect occurred, from among a cell portion, a non-cell portion, a pattern dense portion, and the like according to layout data. Moreover, the defect reviewing apparatus 8 sets inspection parameters, such as pickup magnification of this defect, in response to a result of the identi…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.