Integrated memory arrangement based on resistive memory cells and production method
US7233515B2 · kind B2 · utility
15Cited by
2References
27Claims
0Family size
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Inventor
Key dates
| Filing date | Aug 23, 2005 |
| Grant date | Jun 19, 2007 |
| Priority date | — |
| Expiry date | Dec 5, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B61/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated memory arrangement based on resistive memory cells that can be changed over between a first state of high electrical resistance and a second state of low electrical resistance, each memory cell having an electrical additional capacitance that increases its capacitance, and to a production method.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.