Apparatus and method for handling BTAC branches that wrap across instruction cache lines
US7234045B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 19, 2005 |
| Grant date | Jun 19, 2007 |
| Priority date | — |
| Expiry date | Dec 9, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3806
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A branch control apparatus in a microprocessor. The apparatus includes a branch target address cache (BTAC) that caches indications of whether a branch instruction wraps across two cache lines. When an instruction cache fetch address of a first cache line containing the first part of the branch instruction hits in the BTAC, the BTAC outputs a target address of the branch instruction and indicates the wrap condition. The target address is stored in a register. The next sequential fetch address selects a second cache line containing the second part of the branch instruction. After the two cache lines containing the branch instruction are fetched, the target address from the register is provided to the instruction cache in order to fetch a third cache line containing a target instruction of the branch. The three cache lines are stored in order in an instruction buffer for decoding.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.