Nonvolatile semiconductor memory device with tapered sidewall gate and method of manufacturing the same
US7235441B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 29, 2004 |
| Grant date | Jun 26, 2007 |
| Priority date | — |
| Expiry date | May 10, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/511
Abstract
In a split gate type nonvolatile memory cell in which a MOS transistor for a nonvolatile memory using a charge storing film and a MOS transistor for selecting it are adjacently formed, the charge storing characteristic is improved and the resistance of the gate electrode is reduced. In order to prevent the thickness reduction at the corner portion of the charge storing film and improve the charge storing characteristic, a taper is formed on the sidewall of the select gate electrode. Also, in order to stably perform a silicide process for reducing the resistance of the self-aligned gate electrode, the sidewall of the select gate electrode is recessed. Alternatively, a discontinuity is formed between the upper portion of the self-aligned gate electrode and the upper portion of the select gate electrode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.