Fabrication method for a semiconductor structure and corresponding semiconductor structure

US7235447B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Ulrich Frey · Dresden, DE
• Matthias Goldbach · Dresden, DE
• Dirk Offenberg · Dresden, DE

Key dates

• Filing date: Jan 14, 2005
• Grant date: Jun 26, 2007
• Expiry date: Sep 3, 2025

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/038
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

The present invention provides a fabrication method for a semiconductor structure and a corresponding semiconductor structure. The fabrication method comprises the following steps:provision of a semiconductor substrate (1) with a gate dielectric (5); provision of a plurality of multilayered, elongate gate stacks (GS1; GS2) which essentially run parallel to one another on the gate dielectric (5), which gate stacks have a bottommost layer (10) made of silicon; provision of a first liner layer (60) made of a first material over the gate stacks (GS1; GS2) and the gate dielectric (5) uncovered beside the latter, the thickness (h) of which liner layer is less than a thickness (h′) of the bottommost layer (10) made of silicon; provision of sidewall spacers (70) made of a second material on the vertical sidewalls of the gate stacks (GS1; GS2) over the first liner layer (60), a region of the first liner layer (60) over the gate dielectric (5) between the gate stacks (GS1; GS2) remaining free; selective removal of the first liner layer (60) with respect to the sidewall spacers (70) for the purpose of laterally uncovering the bottommost layer (10) made of silicon of the gate stacks (GS1; GS2)…