Drain extended MOS devices with self-aligned floating region and fabrication methods therefor

US7235451B2 · kind B2 · utility

Assignee

• TEXAS INSTRUMENTS INCORPORATED · US

Inventors

• Pinghai Hao · Plano, US
• Shanjen Pan · Plano, US
• Sameer Pendharkar · Allen, US

Key dates

• Filing date: Mar 3, 2003
• Grant date: Jun 26, 2007
• Expiry date: Mar 3, 2023

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D62/151

Abstract

Semiconductor devices and manufacturing methods therefor are disclosed, in which a drain-extended MOS transistor comprises a self-aligned floating region proximate one end of the transistor gate and doped with a first type dopant to reduce channel hot carrier degradation, as well as an oppositely doped first source/drain laterally spaced from the first end of the gate structure in a semiconductor body. The device may further comprise a resurf region doped to a lower concentration than the floating region to facilitate improved breakdown voltage performance. A method of fabricating a drain-extended MOS transistor in a semiconductor device is disclosed, comprising providing first dopants to a floating region in a semiconductor body, which is self-aligned with the first end of a gate structure, and providing second dopants to source/drains of the semiconductor body, wherein the first and second dopants are different.