Dual silicide semiconductor fabrication process
US7235473B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 26, 2005 |
| Grant date | Jun 26, 2007 |
| Priority date | — |
| Expiry date | Aug 26, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/0213
Abstract
A semiconductor fabrication process includes forming a gate stack overlying semiconductor substrate. Source/drain regions are formed in the substrate laterally aligned to the gate stack. A hard mask is formed overlying a gate electrode of the gate stack. A first silicide is then formed selectively over the source/drain regions. After removing the hard mask, a second silicide is selectively formed on the gate electrode. The first silicide and the second silicide are different. Forming the gate stack may include forming a gate dielectric on the semiconductor substrate and a polysilicon gate electrode on the gate dielectric. The gate electrode may have a line width of less than 40 nm. Forming the second silicide may include forming nickel silicide in upper portions of the gate electrode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.