Device and method to eliminate shorting induced by via to metal misalignment
US7235489B2 · kind B2 · utility
0Cited by
17References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 21, 2004 |
| Grant date | Jun 26, 2007 |
| Priority date | — |
| Expiry date | Oct 4, 2024 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/963
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention provides an interconnect that can be employed in an integrated circuit. The interconnect includes a metal line located over a substrate, a dielectric layer located over the metal line, and an interconnect located in the dielectric layer, including a landed portion located over the metal line and an unlanded portion located along at least a portion of a lateral edge of the metal line. The unlanded portion is at least partially filled with a polymer, and the landed portion is substantially filled with a conductive material. A method for manufacturing the interconnect is also provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.