Integrated circuit package having a resistant layer for stopping flowed glue
US7235869B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 10, 2003 |
| Grant date | Jun 26, 2007 |
| Priority date | — |
| Expiry date | Mar 8, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit package comprises a substrate having an upper surface, a lower surface, and a long slot penetrating from the upper surface to the lower surface. The lower surface is formed with a wiring regioins arranged at side of the long slot, and the wiring regions formed with a plurality of connection points. A glue layer is coated on the upper surface of the substrate and as arranged at the periphery of the long slot. The integrated circuit has a first surface formed with a plurality of bonding pads and is adhered to the glue layer. The wires, each of which is arranged within the long slot of the substrate electrically connected the bonding pads of the integrated circuit to the connection points of the substrate. The first compound layer is filled within the long slot of the substrate to protect the wires.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.