Semiconductor package with improved chip attachment and manufacturing method thereof
US7235887B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 6, 2004 |
| Grant date | Jun 26, 2007 |
| Priority date | — |
| Expiry date | Aug 6, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package comprises a chip having a top surface for chip pads and a bottom surface opposite the top surface. The top and bottom surfaces define side surfaces. The package further includes an adhesive layer provided within a chip-attaching area substantially defined by side surfaces of the chip and attaches a chip to, for example, a substrate having substrate pads. This prevents the contamination of the substrate pads by the adhesive layer. In one embodiment, the adhesive layer has at least one hole formed therethrough to expose a portion of the bottom surface of the chip. The adhesive layer may include at least one passage laterally connecting the hole to the outside. Alternatively, the adhesive layer has a plurality of adhesive parts separately disposed on the semiconductor chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.