Fast dynamic low-voltage current mirror with compensated error
US7236050B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 29, 2006 |
| Grant date | Jun 26, 2007 |
| Priority date | — |
| Expiry date | Mar 29, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG05F3/262
- WIPO fieldControl
- WIPO sectorInstruments
Abstract
A current mirror comprising: a current source; a first p-channel MOS transistor having a source coupled to an operating potential, and a gate and a drain coupled to the current source; a second p-channel MOS transistor having a source coupled to the operating potential, a gate coupled to the gate of the first p-channel transistor, and a drain; a first n-channel MOS transistor having a source coupled to ground, and a gate and a drain coupled to the drain of the second p-channel transistor; a zero-threshold n-channel MOS transistor having a drain coupled to a current-output node, a gate coupled to the gate of the first n-channel transistor, and a source; and a second n-channel MOS transistor having a source coupled to ground, and a gate coupled to the gate of the first n-channel transistor and a drain coupled to the source of the zero-threshold n-channel transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.