Integrated semiconductor memory with redundant memory cells replaceable for either true or complementary defective memory cells

US7236412B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Manfred Proll · Dorfen, DE
• Johann Pfeiffer · Ottobrunn, DE
• Stephan Schröder · Birkenfeld, DE
• Arndt Gruber · Birkenfeld, DE
• Georg Eggers · Birkenfeld, DE

Key dates

• Filing date: Feb 9, 2005
• Grant date: Jun 26, 2007
• Expiry date: Jun 17, 2025

Classification

• Technology area (CPC G): Physics
• CPC primary: G11C29/80
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

An integrated semiconductor memory including memory cells which can be driven via first and second word lines and can be replaced by redundant memory cells. In the first memory cell type, data can be stored corresponding to the data present at a data input terminal. In the memory cells of a second memory cell type, data can be stored inverted with respect to data present at the data input terminal. The integrated semiconductor memory includes a circuit for data inversion, wherein the data are written to a redundant memory cell, inverted with respect to the data present at the data input terminal if the defective memory cell and the redundant memory cell replacing it are situated in different word line strips of a bit line twist, and if the defective memory cell and the redundant memory cell replacing it are associated with different memory cell types.