Method for testing embedded DRAM arrays
US7237165B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 22, 2004 |
| Grant date | Jun 26, 2007 |
| Priority date | — |
| Expiry date | May 18, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/104
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system for testing a DRAM includes DRAM blocks, the system further includes a processor based built-in self test system for generating a test data pattern, for each DRAM block, performing a write of the test data pattern into the DRAM block, performing a pause for a predetermined period of time, and performing a read of a resulting data pattern from the DRAM block. For each DRAM block, the performing the write of the test pattern into the DRAM block is performed before the performing the pause for the predetermined period of time, and the performing the read of the resulting data pattern from the DRAM block is performed after the performing the pause for the predetermined period of time, and at least a portion of the pause for the predetermined period of time of two or more the DRAM blocks overlap in time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.