Methods of fabricating nitride-based transistors with a cap layer and a recessed gate
US7238560B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 23, 2004 |
| Grant date | Jul 3, 2007 |
| Priority date | — |
| Expiry date | May 2, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/513
Abstract
An anneal of a gate recess prior to formation of a gate contact, such as a Schottky contact, may reduce gate leakage and/or provide a high quality gate contact in a semiconductor device, such as a transistor. The use of an encapsulation layer during the anneal may further reduce damage to the semiconductor in the gate recess of the transistor. The anneal may be provided, for example, by an anneal of ohmic contacts of the device. Thus, high quality gate and ohmic contacts may be provided with reduced degradation of the gate region that may result from providing a recessed gate structure as a result of etch damage in forming the recess.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.