Method of manufacturing a semiconductor device with a strained channel
US7238581B2 · kind B2 · utility
2Cited by
4References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 16, 2004 |
| Grant date | Jul 3, 2007 |
| Priority date | — |
| Expiry date | Oct 9, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
Abstract
A method of manufacturing a semiconductor device provides a semiconductor substrate with a gate and a number of source/drain regions on the semiconductor substrate. A layer containing a strain-inducing element is provided over the number of source/drain regions. The strain-inducing element is driven from the layer containing a strain-inducing element into the number of source/drain regions. A number of source/drains is formed in the number of source/drain regions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.