Jinping Liu
101Patents
9h-index
191Co-inventors
83Inventor score
Filing activity: Oct 16, 1990 → May 7, 2022
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US7169675B2 | Material architecture for the fabrication of low temperature transistor | Electricity | 149 | Expired |
| US7109099B2 | End of range (EOR) secondary defect engineering using substitutional carbon doping | Electricity | 99 | Expired |
| US9105497B2 | Methods of forming gate structures for transistor devices for CMOS applications | Electricity | 15 | Active |
| US9159794B2 | Method to form wrap-around contact for finFET | Electricity | 14 | Active |
| US9553194B1 | Method for improved fin profile | Electricity | 13 | Active |
| US10062692B1 | Field effect transistors with reduced parasitic resistances and method | Electricity | 13 | Active |
| US9805982B1 | Apparatus and method of adjusting work-function metal thickness to provide variable threshold voltages in finFETs | Electricity | 13 | Active |
| US9455204B1 | 10 nm alternative N/P doped fin for SSRW scheme | Electricity | 13 | Active |
| US9711447B1 | Self-aligned lithographic patterning with variable spacings | Electricity | 9 | Active |
| US9947769B1 | Multiple-layer spacers for field-effect transistors | Electricity | 9 | Active |
| US9330982B1 | Semiconductor device with diffusion barrier film and method of manufacturing the same | Electricity | 7 | Active |
| US8058123B2 | Integrated circuit and method of fabrication thereof | Electricity | 7 | Active |
| US9640423B2 | Integrated circuits and methods for their fabrication | Electricity | 7 | Active |
| US9589807B1 | Method for eliminating interlayer dielectric dishing and controlling gate height uniformity | Electricity | 7 | Active |
| US9362283B2 | Gate structures for transistor devices for CMOS applications and products | Electricity | 6 | Active |
| US10192780B1 | Self-aligned multiple patterning processes using bi-layer mandrels and cuts formed with block masks | Electricity | 6 | Active |
| US9761452B1 | Devices and methods of forming SADP on SRAM and SAQP on logic | Electricity | 6 | Active |
| US8012839B2 | Method for fabricating a semiconductor device having an epitaxial channel and transistor having same | Electricity | 6 | Active |
| US5631374A | Reagents for detection of primary amines | Emerging Cross-Sectional Technologies | 5 | Expired |
| US9577066B1 | Methods of forming fins with different fin heights | Electricity | 5 | Active |
| US9773680B1 | Advanced method for scaled SRAM with flexible active pitch | Electricity | 5 | Active |
| US10347541B1 | Active gate contacts and method of fabrication thereof | Electricity | 4 | Active |
| US8637372B2 | Methods for fabricating a FINFET integrated circuit on a bulk silicon substrate | Electricity | 4 | Active |
| US10312150B1 | Protected trench isolation for fin-type field-effect transistors | Electricity | 4 | Active |
| US10586860B2 | Method of manufacturing finfet devices using narrow and wide gate cut openings in conjunction with a replacement metal gate process | Electricity | 4 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.