Interlayer dielectric under stress for an integrated circuit

US7238990B2 · kind B2 · utility

Assignee

• Freeescale Semiconductor, Inc. · US

Inventors

• James D. Burnett · Austin, US
• Jon D. Cheek · Wallkill, US

Key dates

• Filing date: Apr 6, 2005
• Grant date: Jul 3, 2007
• Expiry date: Sep 28, 2025

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y10S257/903

Abstract

An integrated circuit that has logic and a static random access memory (SRAM) array has improved performance by treating the interlayer dielectric (ILD) differently for the SRAM array than for the logic. The N channel logic and SRAM transistors have ILDs with non-compressive stress, the P channel logic transistor ILD has compressive stress, and the P channel SRAM transistor at least has less compressive stress than the P channel logic transistor, i.e., the P channel SRAM transistors may be compressive but less so than the P channel logic transistors, may be relaxed, or may be tensile. It is beneficial for the integrated circuit for the P channel SRAM transistors to have a lower mobility than the P channel logic transistors. The P channel SRAM transistors having lower mobility results in better write performance; either better write time or write margin at lower power supply voltage.