Multiple power levels for a chip within a multi-chip semiconductor package
US7240254B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 25, 2004 |
| Grant date | Jul 3, 2007 |
| Priority date | — |
| Expiry date | Feb 13, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/49175
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory chip is provided for packaging along with a system chip in a single semiconductor package having a plurality of external connectors. The memory chip includes a memory storage array for storing data. A plurality of data buffers is provided for writing or reading data between said memory storage array and the system chip within the single semiconductor package. A first power level may be used for each of the plurality of data buffers. At least one test buffer is directly connected to certain of said plurality of external connectors for supporting testing of said memory chip within the single semiconductor package by external test equipment. A second power level may be used for the test buffer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.