Silicon wafers and method of fabricating the same
US7242075B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Oct 31, 2003 |
| Grant date | Jul 10, 2007 |
| Priority date | — |
| Expiry date | Oct 31, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/3225
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
By using a two-step RTP (rapid thermal processing) process, the wafer is provided which has an ideal semiconductor device region secured by controlling fine oxygen precipitates and OiSFs (Oxidation Induced Stacking Fault) located on the surface region of the wafer. By performing the disclosed two-step rapid thermal process, the distribution of defects can be accurately controlled and an ideal device active zone can be formed up to a certain distance from the surfaces of the wafer. In addition, it is possible to maximize the internal gettering (IG) efficiency by enabling the oxygen precipitates and the bulk stacking faults to have constant densities in the depth direction in an internal region of the wafer, that is, the bulk region. In order to obtain the constant concentration profile of the oxygen precipitates and the bulk stacking faults in the bulk region, the wafer is subjected to the aforementioned two-step rapid thermal process in a predetermined mixed gas atmosphere.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.