System and method for testing one or more dies on a semiconductor wafer
US7242208B2 · kind B2 · utility
3Cited by
11References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 22, 2006 |
| Grant date | Jul 10, 2007 |
| Priority date | — |
| Expiry date | Mar 22, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/2602
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A testing system or method compares read data from one or more dies in a semiconductor wafer with the original data written onto the one or more dies. The testing system includes one or more write registers connected to one or more dies on the semiconductor wafer. One or more comparators are connected to the dies and the write registers. The comparator generates a result in response to the original data and the read data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.