Fast dynamic low-voltage current mirror with compensated error
US7242242B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 29, 2006 |
| Grant date | Jul 10, 2007 |
| Priority date | — |
| Expiry date | Mar 29, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG05F3/262
- WIPO fieldControl
- WIPO sectorInstruments
Abstract
A current mirror comprising: current source; a first p-channel transistor having a source coupled to operating potential, and a gate and drain coupled to current source; a second p-channel transistor having a source coupled to operating potential, a gate coupled to gate of first p-channel transistor, and a drain; a zero-threshold p-channel transistor having a source coupled to drain of second p-channel transistor, a gate coupled to gate of first p-channel transistor, and a drain; a first n-channel transistor having a source coupled to ground, and a gate and drain coupled to drain of zero-threshold p-channel transistor; a second n-channel transistor having a source coupled to ground, a gate coupled to gate of first n-channel transistor, and a drain; and a zero-threshold n-channel transistor having a source coupled to drain of second n-channel transistor, a gate coupled to gate of first n-channel transistor, and a drain coupled to current-output node.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.