Floating-gate MOS transistor with double control gate
US7242621B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Jun 17, 2005 |
| Grant date | Jul 10, 2007 |
| Priority date | — |
| Expiry date | Jul 16, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6892
Abstract
The present invention relates to a floating-gate MOS transistor, comprising drain and source regions implanted into a silicon substrate, a channel extending between the drain and source regions, a tunnel oxide, a floating gate, a gate oxide and a control gate extending according to a determined gate length. According to the present invention, the control gate comprises a small gate and a large gate arranged side by side and separated by an electrically insulating material. Application to the production of memory cells without access transistor, and to the implementation of an erase-program method with reduced electrical stress for the tunnel oxide.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.