Integrated circuit tester with software-scaleable channels
US7243278B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 14, 2005 |
| Grant date | Jul 10, 2007 |
| Priority date | — |
| Expiry date | Nov 24, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31921
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
An integrated circuit tester for testing an IC device under test (DUT) during a succession of test cycles includes a pattern generator programmed to generate data before each test cycle encoded to specify all test activities to be carried out during the test cycle and to specify for each test activity a time during the test cycle at which the test activity is to be carried out and a DUT IO pin at which the test activity is to be carried out. Multiple programmable tester channels each comprise multiple DUT interface circuits, each of which can be connected to a separate DUT IO pin for carrying out test activities at that DUT IO pin when signaled to do so, and hardware resources programmed by decoding instructions to decode the data from the pattern generator for each test cycle and initiate each specified test activity by signaling the DUT interface circuit that is specified for the test activity at the time specified for the test activity.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.