Undercut and residual spacer prevention for dual stressed layers

US7244644B2 · kind B2 · utility

Assignees

• International Business Machines Corporation · US
• Advanced Micro Devices, Inc. · US

Inventors

• Huilong Zhu · Poughkeepsie, US
• Brian L. Tessier · Poughkeepsie, US
• Huicai Zhong · San Jose, US
• Ying Li · Potsdam, US

Key dates

• Filing date: Jul 21, 2005
• Grant date: Jul 17, 2007
• Expiry date: Jul 21, 2025

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/0167

Abstract

Methods are disclosed for forming dual stressed layers in such a way that both undercutting and an undesirable residual spacer of the first-deposited stressed layer are prevented. In one embodiment, a method includes forming a first stressed silicon nitride layer over the NFET and the PFET, forming a sacrificial layer over the first stressed silicon nitride layer such that the sacrificial layer is thinner over substantially vertical surfaces than over substantially horizontal surfaces, forming a mask over a first one of the NFET and the PFET, removing the first stressed silicon nitride layer over a second one of the NFET and the PFET, and forming a second stressed silicon nitride layer over the second one of the NFET and the PFET. The sacrificial layer prevents undercutting and forming of an undesirable residual spacer during removal of the first-deposited stressed layer.