Brian L. Tessier
14Patents
4h-index
25Co-inventors
56Inventor score
Filing activity: Jul 18, 2002 → Dec 16, 2016
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6900519B2 | Diffused extrinsic base and method for fabrication | Electricity | 96 | Expired |
| US6774000B2 | Method of manufacture of MOSFET device with in-situ doped, raised source and drain structures | Electricity | 38 | Expired |
| US6858903B2 | MOSFET device with in-situ doped, raised source and drain structures | Electricity | 15 | Expired |
| US7244644B2 | Undercut and residual spacer prevention for dual stressed layers | Electricity | 10 | Expired |
| US7459382B2 | Field effect device with reduced thickness gate | Electricity | 4 | Active |
| US6869854B2 | Diffused extrinsic base and method for fabrication | Electricity | 3 | Expired |
| US7718514B2 | Method of forming a guard ring or contact to an SOI substrate | Electricity | 3 | Active |
| US7888738B2 | Method of forming a guard ring or contact to an SOI substrate | Electricity | 3 | Active |
| US7358172B2 | Poly filled substrate contact on SOI structure | Electricity | 2 | Active |
| US7485521B2 | Self-aligned dual stressed layers for NFET and PFET | Emerging Cross-Sectional Technologies | 2 | Active |
| US7776695B2 | Semiconductor device structure having low and high performance devices of same conductive type on same substrate | Electricity | 1 | Active |
| US10224414B2 | Method for providing a low-k spacer | Electricity | 0 | Active |
| US7592245B2 | Poly filled substrate contact on SOI structure | Electricity | 0 | Active |
| US8492803B2 | Field effect device with reduced thickness gate | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.