Multi-layer integrated circuit package
US7245001B2 · kind B2 · utility
0Cited by
8References
11Claims
0Family size
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Key dates
| Filing date | Aug 11, 2004 |
| Grant date | Jul 17, 2007 |
| Priority date | — |
| Expiry date | Nov 21, 2024 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49128
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
Adhesive material is applied to a surface of a metallic core layer. The adhesive material is removed from a conductive region of the metallic core layer. A metallic contact is provided over the conductive region of the metallic core layer. The metallic core layer is laminated to an imprinted buildup layer, the buildup layer having a dielectric region and a conductive region, wherein a nonconductive region of the metallic core layer is bonded to the dielectric region of the buildup layer and the conductive region of the metallic core layer is bonded to the conductive region of the imprinted-buildup layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.