Shared bond pad for testing a memory within a packaged semiconductor device
US7245141B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 9, 2005 |
| Grant date | Jul 17, 2007 |
| Priority date | — |
| Expiry date | Sep 12, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/48137
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A system is provided for communicating with a device within a packaged semiconductor device through a shared external terminal thereof. As one example, the system provides for testing a memory within the package. In addition to the device and the shared external terminal, the system includes a command register that receives a plurality of command signals, and digital logic devices coupled between the external terminal and the command register. Each of the digital logic devices receives a different clock signal and outputs one of the command signals to the command register. The command signals are provided to the external terminal in a sequence that is coordinated with the clock signals so that each digital logic device buffers one of the command signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.