Method of automatic fault isolation in a programmable logic device

US7246285B1 · kind B1 · utility

Assignee

• XILINX, INC. · US

Inventors

• Tarek Eldin · San Jose, US
• Zhi-Min Ling · Cupertino, US
• Feng Wang · 红钢城街道, CN
• David M. Mahoney · Palo Alto, US

Key dates

• Filing date: Apr 1, 2004
• Grant date: Jul 17, 2007
• Expiry date: Mar 26, 2025

Classification

• Technology area (CPC G): Physics
• CPC primary: G01R31/31717
• WIPO field: Measurement
• WIPO sector: Instruments

Abstract

The configuration of a faulty line segment in a switch matrix of a programmable logic device is identified using read-back capture. Each original programmable interconnection point (“PIP”) in the line segment is tested by generating routes from a first logic port through the original line segment and PIP, through all PIPs, adjacent to the original PIP to the opposite logic port. Routes through all PIPs adjacent to the PIPs in the line segment from the first logic port to the second logic port, and from the second logic port to the first logic port, are tested to isolate the fault in the line segment.