Method to control dual damascene trench etch profile and trench depth uniformity
US7247555B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 29, 2004 |
| Grant date | Jul 24, 2007 |
| Priority date | — |
| Expiry date | Apr 14, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76808
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming trench openings in a dual damascene trench and via etch process by using a two component hard mask layer, termed a bi-layer, over different intermetal dielectrics, IMD, to solve dual damascene patterning problems, such as, fencing and sub-trench formation. Via first patterning in dual damascene processing is one of the major integration schemes for copper backend of line (BEOL) integration. Via first dual damascene scheme usually uses a hard mask layer deposited on top of an inter-metal dielectric (IMD) film stack. The dual damascene trench etch requires uniform trench depth across wafer after etch. In addition, via top corner profiles need to be well maintained without any fencing or faceting. The present method solves these problems by using a two component hard mask layer, termed a bi-layer, deposited directly on top of an inter-metal dielectric (IMD) film stack.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.