Bidirectional split gate NAND flash memory structure and array, method of programming, erasing and reading thereof, and method of manufacturing
US7247907B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 20, 2005 |
| Grant date | Jul 24, 2007 |
| Priority date | — |
| Expiry date | Jul 26, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B41/27
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A split gate NAND flash memory structure is formed on a semiconductor substrate of a first conductivity type. The NAND structure comprises a first region of a second conductivity type and a second region of the second conductivity type in the substrate, spaced apart from the first region, thereby defining a channel region therebetween. A plurality of floating gates are spaced apart from one another and each is insulated from the channel region. A plurality of control gates are spaced apart from one another, with each control gate insulated from the channel region. Each of the control gate is between a pair of floating gates and is capacitively coupled to the pair of floating gates. A plurality of select gates are spaced apart from one another, with each select gate insulated from the channel region. Each select gate is between a pair of floating gates.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.