Inventor · Saratoga, CA, US

Ya-Fen Lin

22Patents
6h-index
21Co-inventors
65Inventor score

Filing activity: Mar 9, 2004 → Feb 14, 2022

Most-cited inventions

PatentTitleAreaCited byStatus
US7050316B1 Differential non-volatile content addressable memory cell and array using phase changing resistor storage elements Physics 66 Expired
US7403418B2 Word line voltage boosting circuit and a memory array incorporating same Physics 35 Expired
US7247907B2 Bidirectional split gate NAND flash memory structure and array, method of programming, erasing and reading thereof, and method of manufacturing Electricity 14 Expired
US8692310B2 Gate fringing effect based channel formation for semiconductor device Electricity 7 Active
US8638609B2 Partial local self boosting for NAND Physics 6 Active
US7544569B2 Bidirectional split gate NAND flash memory structure and array, method of programming, erasing and reading thereof, and method of manufacturing Electricity 6 Active
US7351613B2 Method of trimming semiconductor elements with electrical resistance feedback Electricity 5 Expired
US7242051B2 Split gate NAND flash memory structure and array, method of programming, erasing and reading thereof, and method of manufacturing Physics 5 Expired
US8780642B2 Split gate NAND flash memory structure and array, method of programming, erasing and reading thereof, and method of manufacturing Physics 4 Active
US7723774B2 Non-diffusion junction split-gate nonvolatile memory cells and arrays, methods of programming, erasing, and reading thereof, and methods of manufacture Electricity 3 Active
US9570458B2 Gate fringing effect based channel formation for semiconductor device Electricity 3 Active
US9449693B2 Split gate NAND flash memory structure and array, method of programming, erasing and reading thereof, and method of manufacturing Physics 2 Active
US7826267B2 Method and apparatus for reading and programming a non-volatile memory cell in a virtual ground array Physics 2 Active
US8164135B2 Non-diffusion junction split-gate nonvolatile memory cells and arrays, methods of programming, erasing, and reading thereof, and methods of manufacture Electricity 2 Active
US9514824B2 Partial local self boosting for NAND Physics 1 Active
US7848146B2 Partial local self-boosting of a memory cell channel Physics 1 Active
US11251189B2 Gate fringing effect based channel formation for semiconductor device Electricity 0 Active
US9892790B2 Method of programming a continuous-channel flash memory device Physics 0 Active
US7790518B2 Method of trimming semiconductor elements with electrical resistance feedback Electricity 0 Active
US7808839B2 Split gate NAND flash memory structure and array, method of programming, erasing and reading thereof, and method of manufacturing Physics 0 Active
US10297606B2 Gate fringing effect based channel formation for semiconductor device Electricity 0 Active
US11950412B2 Gate fringing effect based channel formation for semiconductor device Electricity 0 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.