Thin multiple semiconductor die package

US7247933B2 · kind B2 · utility

Assignee

• Advanced Interconnect Technologies Limited · MU

Inventors

• Frank J. Juskey · Coral Springs, US
• Daniel Lau · San Francisco, US

Key dates

• Filing date: Feb 3, 2004
• Grant date: Jul 24, 2007
• Expiry date: Feb 3, 2024

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/18165
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A method and apparatus for forming a multiple semiconductor die assembly (200, 300, 400) having a thin profile are presented. The semiconductor die assembly (200, 300, 400) comprises a plurality of die packages (100), with each die package (100) including a lead frame (10) having a plurality of leads (11) each having a down set portion (101) extending from (14). A semiconductor die (30) is disposed in a central region (12) of the lead frame (10) and is electrically connected (11). An encapsulant (50) is disposed in the central region (12) and covers to the semiconductor die (30) and a portion (11). The first surface (14) of the leads (11) and a first surface (34) of the semiconductor die (30) are substanial exposed from the encapsulant (50). The first surface (34) of the semiconductor die (30) and the down set portions (101) form a cavity (102). The semiconductor die packages (200, 300, 400) are stacked such that at least a portion of the encapsulant (50) is disposed in the cavity of a next higher semiconductor die package (200, 300, 400) in the stack.