Multi-chip semiconductor package
US7247934B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 29, 2004 |
| Grant date | Jul 24, 2007 |
| Priority date | — |
| Expiry date | Dec 29, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2201/10689
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A multi-chip semiconductor package and a fabrication method thereof are provided. At least one first chip is mounted on and electrically connected to an upper surface of a substrate via solder bumps. A preformed package structure having a second chip and a first encapsulation body is mounted on the upper surface of the substrate, wherein outer leads of the preformed package structure are exposed from the first encapsulation body and electrically connected to the upper surface of the substrate. The first encapsulation body, outer leads and substrate form a space where the first chip is received, and a gap is present between the first chip and the first encapsulation body. A second encapsulation body is formed on the upper surface of the substrate to encapsulate the first chip, solder bumps and preformed package structure. A plurality of solder balls are implanted on the lower surface of the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.