Integrated semiconductor memory and method for operating an integrated semiconductor memory
US7248536B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 6, 2005 |
| Grant date | Jul 24, 2007 |
| Priority date | — |
| Expiry date | Jan 13, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/1202
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory and a method for operating the latter in order are provided, at least in testwise fashion, to deactivate a word line segment (12) of a segmented word line not via a first line (21) otherwise used for deactivation, but rather via a second line (22) via that the word line segment (12) is otherwise activated. The second line (22) can optionally be biased with a second potential (Vpp) provided for activation or with a third potential (Vgnd). If the third potential (Vgnd) is used for at least temporarily deactivating the word line segment (12), the word line segment can be driven via a switching element (17), which couples the word line segment to the second line (22), without the complementary switching element (16) of the driver segment (20) having to be used for deactivation. It can thereby be ascertained which of two switching elements (16, 17) of the driver segment is defective and whether or not the semiconductor memory will function in a manner free of errors after permanent replacement of the word line on account of a floating potential of the tested word line segment (12).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.