Methods of estimating susceptibility to single event upsets for a design implemented in an FPGA
US7249010B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 3, 2003 |
| Grant date | Jul 24, 2007 |
| Priority date | — |
| Expiry date | Mar 16, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2117/02
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods of estimating the susceptibility to single event upsets (SEUs) of a design implemented in an FPGA. In an FPGA, many of the configuration memory cells could change state in response to an SEU without affecting the functionality of a design implemented in the FPGA. According to the methods of the invention, the number of “care bits” (bits associated with resources actually used in the design) is determined. The number of care bits as a proportion of the total number of configuration memory cells in the FPGA determines the “SEU Probability Impact” (SEUPI) value. The “Mean Time Between Upsets” (MTBU) value is an estimate of how much time will elapse, on average, before one of the configuration memory cells in the FPGA is affected by an SEU. To obtain the “Mean Time Between Failures” for the design implemented in the FPGA, the MTBU value is divided by the SEUPI value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.