Method for forming metal silicide regions in an integrated circuit
US7250356B2 · kind B2 · utility
0Cited by
9References
5Claims
0Family size
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Key dates
| Filing date | Sep 17, 2002 |
| Grant date | Jul 31, 2007 |
| Priority date | — |
| Expiry date | Sep 17, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/28518
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming a metal silicide region in a silicon region of a semiconductor substrate. The method comprises forming a metal layer over the silicon region, then in succession forming a titanium and a titanium nitride layer thereover. As the substrate is heated to form the silicide, the titanium getters silicon dioxide on the surface of the silicon region and the titanium nitride promotes the formation of a smooth surface at the interface between the silicide layer and the underlying silicon region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.