Non-volatile memory device
US7250654B2 · kind B2 · utility
39Cited by
3References
29Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 7, 2005 |
| Grant date | Jul 31, 2007 |
| Priority date | — |
| Expiry date | Nov 7, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/40
Abstract
A single-poly non-volatile memory device invented to integrate into logic process is disclosed. This non-volatile memory device includes a memory cell unit comprising a PMOS access transistor that is serially connected to a PMOS storage transistor formed in a cell array area, and, in a peripheral circuit area, a high-voltage MOS transistor having a high-voltage gate insulation layer is provided. The PMOS access transistor has an access gate oxide layer that has a thickness equal to the thickness of the high-voltage gate insulation layer in a peripheral circuit area.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.