Dual semiconductor die package with reverse lead form
US7250672B2 · kind B2 · utility
15Cited by
7References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 12, 2004 |
| Grant date | Jul 31, 2007 |
| Priority date | — |
| Expiry date | Feb 25, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package that includes two semiconductor die each disposed on a respective die pad and a large tracking distance interposed between at least two leads of the package for better creepage characteristics.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.