Memory check architecture and method for a multiprocessor computer system
US7251744B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 21, 2004 |
| Grant date | Jul 31, 2007 |
| Priority date | — |
| Expiry date | Feb 10, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/2284
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and apparatus are provided for use in testing a memory (220, 230, 240) in a multiprocessor computer system (200). The multiprocessor computer system (200) has a plurality of processing nodes (210-217) coupled in an array wherein each processing node is coupled to at least one other processing node, and a memory (220, 230, 240) distributed among the plurality of processing nodes (210-217). A configuration of the array is determined. An initial configuration of the memory (220, 230, 240) is also determined. The memory (220, 230, 240) is tested over the array according to the initial configuration to identify a bad memory element. The initial configuration is modified to form a revised configuration that excludes the bad memory element.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.