Method for fabricating dual work function metal gates
US7253049B2 · kind B2 · utility
7Cited by
3References
30Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 20, 2004 |
| Grant date | Aug 7, 2007 |
| Priority date | — |
| Expiry date | Aug 13, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/68
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for making PMOS and NMOS transistors 60, 70 on a semiconductor substrate 20 that includes having a gate protection layer 210 over the gate electrode layer 110 during the formation of source/drain silicides 120. The method may include implanting dopants into a gate polysilicon layer 115 before forming the protection layer 215.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.