Integrated circuit system using dual damascene process
US7253097B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 30, 2005 |
| Grant date | Aug 7, 2007 |
| Priority date | — |
| Expiry date | Jun 30, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76846
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit system includes providing a semiconductor substrate having a semiconductor device provided thereon. A first dielectric layer is formed over the semiconductor substrate, and a first conductor core is formed in the first dielectric layer. A stop layer is formed over the first conductor core. A second dielectric layer is formed over the stop layer. A channel and a via are formed in the second dielectric layer. The channel and the via in the second dielectric layer are wet cleaned. A barrier metal layer is deposited to line the channel and the via in the second dielectric layer. The barrier metal layer is selectively etched from the bottom of the via in the dielectric layer, and a second conductor core is formed over the barrier metal layer to fill the second channel and the via to connect the second conductor core to the first conductor core.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.