Method for producing gate stack sidewall spacers
US7253123B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 10, 2005 |
| Grant date | Aug 7, 2007 |
| Priority date | — |
| Expiry date | Oct 24, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/0227
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming sidewall spacers on a gate stack by depositing one or more layers of silicon containing materials using PECVD process(es) on a gate structure to produce a spacer having an overall k value of about 3.0 to about 5.0. The silicon containing materials may be silicon carbide, oxygen doped silicon carbide, nitrogen doped silicon carbide, carbon doped silicon nitride, nitrogen doped silicon oxycarbide, or combinations thereof. The deposition is performed in a plasma enhanced chemical vapor deposition chamber and the deposition temperature is less than 450° C. The sidewall spacers so produced provide good capacity resistance, as well as excellent structural stability and hermeticity.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.