Memory circuit and method for reading out a memory datum from such a memory circuit
US7254052B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 25, 2005 |
| Grant date | Aug 7, 2007 |
| Priority date | — |
| Expiry date | Nov 25, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/79
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention relates to a memory circuit comprising a CBRAM resistance memory cell, which is connected to a bit line and a word line and has a CBRAM resistance element, the resistance of which can be set by means of a write current, in order to store an item of information, and which has a selection switch, which can be driven via the word line, in order to connect a first potential to the bit line via the CBRAM resistance element; a reference resistance cell, which is connected to the bit line and to a reference line and has a reference resistance element, the resistance of which is set to a resistance threshold value, and a reference selection switch, which can be driven via the reference line, in order to connect a second potential to the bit line via the reference resistance element; a read-out unit, which is configured to activate the reference selection switch and the selection switch for the purpose of reading out a memory datum, so that a memory cell current flows via the CBRAM resistance memory cell and a reference current flows via the reference resistance cell onto the bit line; and an evaluation unit, which is connected to the bit line, and which outputs the me…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.