Method and apparatus for testing circuit units to be tested with different test mode data sets
US7254758B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 12, 2005 |
| Grant date | Aug 7, 2007 |
| Priority date | — |
| Expiry date | May 27, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/56
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The invention provides a test apparatus for testing a circuit unit to be tested. In one embodiment, a circuit unit incorporating aspects of the invention includes a data memory bank (106) for storing test mode data which are fed via an address control terminal (201) and with which the circuit unit (101) to be tested can be tested, provision being made of at least one test mode bank (104a-104n) for providing at least one test mode data set (204a-204n) and at least one activation signal (205a-205n), at least one register bank (103a-103n) and a transfer device for transferring a test mode data set (204a-204n) from a register bank (103a-103n) to the data memory bank (106) in a manner dependent on the activation signal (205a-205n).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.