Method for fabricating integrated circuits having both high voltage and low voltage devices
US7256092B2 · kind B2 · utility
7Cited by
2References
12Claims
0Family size
Assignee
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Key dates
| Filing date | Jul 25, 2004 |
| Grant date | Aug 14, 2007 |
| Priority date | — |
| Expiry date | Jul 17, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/601
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A high-voltage semiconductor MOS process that is fully compatible with low-voltage MOS process is provided. The high-voltage N/P well are implanted into the substrate prior to the definition of active areas. The channel stop doping regions are formed after the formation of field oxide layers, thus avoiding lateral diffusion of the channel stop doping regions. In addition, the grade drive-in process used to activate the grade doping regions in the high-voltage device area and the gate oxide growth of the high-voltage devices are performed simultaneously.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.