Damascene process for use in fabricating semiconductor structures having micro/nano gaps
US7256107B2 · kind B2 · utility
36Cited by
3References
19Claims
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Key dates
| Filing date | May 3, 2005 |
| Grant date | Aug 14, 2007 |
| Priority date | — |
| Expiry date | Aug 24, 2025 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/933
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
In fabricating a microelectromechanical structure (MEMS), a method of forming a narrow gap in the MEMS includes a) depositing a layer of sacrificial material on the surface of a supporting substrate, b) photoresist masking and at least partially etching the sacrificial material to form at least one blade of sacrificial material, c) depositing a structural layer over the sacrificial layer, and d) removing the sacrificial layer including the blade of the sacrificial material with a narrow gap remaining in the structural layer where the blade of sacrificial material was removed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.